Hardmasks are employed as etch masks for a variety of semiconductor manufacturing processes. Titanium nitride (TiN) hardmasks have been used, for example, for forming self-aligned vertical interconnect accesses (VIAs) (the simultaneous formation of a first layer metal and upper layer metal pattern and level (V0 and others) VIAs). However, TiN hardmask layers have poor etch resistance. The poor etch resistance prevents the hardmask layers from being used in processes related to, for example, trench first metal hardmask schemes, hardmask open schemes, and VIA double patterning schemes. Current conventional hardmask layers are also plagued by poor self-aligned VIA (SAV) performance as part of a dielectric etch. A marginal increase in the etch resistance of the hardmask layer will allow for critical functions like merged VIAs to be used with respect to new technology nodes. Merged VIAs will allow designers to fit more VIAs into a fixed space with no upgrade in lithography tool sets.
A need therefore exists for methodology enabling formation of hardmask layers with increased etch resistance and hardmask layer performance, and the resulting device.